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Friday, October 7, 2011

Design and verify half subtractor by using dataflow style .

HALF SUBTRACTOR
( DATAFLOW STYLE )


AIM:


Design and verify half subtractor by using dataflow style .


PROGRAM:
Library ieee;
use ieee.std_logic_1164.all;
entity hs1 is
port(a,b:in bit;d,bo:out bit);
end hs1;
architecture hs1 of hs1 is
begin
d<=a xor b;
bo<=(not a) and b;
end hs1;

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