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Friday, October 7, 2011

Design and verify half adder by using dataflow style .

HALF ADDER
( DATAFLOW STYLE)


AIM:


Design and verify half adder by using dataflow style .


PROGRAM:
Library ieee;
use ieee.std_logic_1164.all;
entity ha1 is
port(a,b:in bit;s,c:out bit);
end ha1;
architecture ha1 of ha1 is
begin
s<=a xor b;
c<=a and b;
end ha1;


SIMULATION OUTPUT:




RESULT: Half adder is sim ulated and verified

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