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Friday, October 7, 2011

Design and verify full subtractor by using dataflow style .

FULL SUBTRACTOR
( DATAFLOW STYLE )


AIM:


Design and verify full subtractor by using dataflow style .


PROGRAM:
library ieee;
use ieee.std_logic_1164.all;
entity f s1 is
port(a,b,c:in bit;d,bo:out bit);
end fs1;
architecture fs1 of fs1 is
begin
d<=a xor b xor c;
bo<=((not a)and b)or(b xor c);
end fs1;

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