## Monday, April 4, 2011

### STUDY OF FLIP FLOPS

STUDY OF FLIP FLOPS

AIM:

To verify the characteristic table of RS, D, JK, and T Flip flops .

APPARATUS REQUIRED:

 S.No Name of the Apparatus Range Quantity 1. Digital IC trainer kit 1 2. NOR gate IC 7402 3. NOT gate IC 7404 4. AND gate ( three input ) IC 7411 5. NAND gate IC 7400 6. Connecting wires As required

THEORY:

A Flip Flop is a sequential device that samples its input signals and changes its output states only at times determined by clocking signal.  Flip Flops may vary in the number of inputs they possess and the manner in which the inputs affect the binary states.

RS FLIP FLOP:

The clocked RS flip flop consists of NAND gates and the output changes its state with respect to the input on application of clock pulse.  When the clock pulse is high the S and R inputs reach the second level NAND gates in their complementary form.   The Flip Flop is reset when the R input  high and S input is low.  The Flip Flop is set when the S input is high and R input is low.  When both the inputs are high the output is in an indeterminate state.

D FLIP FLOP:

To eliminate the undesirable condition of indeterminate state in the SR Flip Flop when both inputs are high at the same time, in the D Flip Flop the inputs are never made equal at the same time.  This is obtained by making the two inputs complement of each other.

JK FLIP FLOP:

The indeterminate state in the SR Flip-Flop is defined in the JK Flip Flop.  JK inputs behave like S and R inputs to set and reset the Flip Flop.  The output Q is ANDed with K input and the clock pulse, similarly the output  Q’ is ANDed with J  input and the Clock pulse.  When the clock pulse is zero both the AND gates are disabled and the Q and Q’ output retain their previous values.  When the clock pulse is high, the J and K inputs reach the NOR gates.  When both the inputs are high the output toggles continuously.  This is called Race around condition and this must be avoided.
T FLIP FLOP:

This is a modification of JK Flip Flop, obtained by connecting both inputs J and K inputs together.  T Flip Flop is also called Toggle Flip Flop.

RS FLIP FLOP

LOGIC SYMBOL:

CIRCUIT DIAGRAM:

CHARACTERISTIC TABLE:

 CLOCKPULSE INPUT PRESENTSTATE (Q) NEXTSTATE(Q+1) STATUS S R 1 0 0 0 0 2 0 0 1 1 3 0 1 0 0 4 0 1 1 0 5 1 0 0 1 6 1 0 1 1 7 1 1 0 X 8 1 1 1 X
D FLIP FLOP

LOGIC SYMBOL:

CIRCUIT DIAGRAM:

CHARACTERISTIC TABLE:

 CLOCKPULSE INPUTD PRESENTSTATE (Q) NEXTSTATE(Q+1) STATUS 1 0 0 0 2 0 1 0 3 1 0 1 4 1 1 1

JK FLIP FLOP

LOGIC SYMBOL:

CIRCUIT DIAGRAM:

CHARACTERISTIC TABLE:

 CLOCKPULSE INPUT PRESENTSTATE (Q) NEXTSTATE(Q+1) STATUS J K 1 0 0 0 0 2 0 0 1 1 3 0 1 0 0 4 0 1 1 0 5 1 0 0 1 6 1 0 1 1 7 1 1 0 1 8 1 1 1 0

T FLIP FLOP

LOGIC SYMBOL:

CIRCUIT DIAGRAM:

CHARACTERISTIC TABLE:

 CLOCKPULSE INPUTT PRESENTSTATE (Q) NEXTSTATE(Q+1) STATUS 1 0 0 0 2 0 1 0 3 1 0 1 4 1 1 0

PROCEDURE:

1. Connections are given as per the circuit diagrams.
2. For all the ICs 7th  pin is grounded and 14th pin is given +5 V supply.
3. Apply the inputs and observe the status of all the flip flops.

RESULT:

The Characteristic tables of RS, D, JK, T flip flops were verified.