## Monday, April 4, 2011

AIM:

To design and verify the truth table of the Half Adder & Full Adder circuits.

APPARATUS REQUIRED:

 S.No Name of the Apparatus Range Quantity 1. Digital IC trainer kit 1 2. AND gate IC 7408 3. OR gate IC 7432 4. NOT gate IC 7404 5. EX-OR gate IC 7486 6. Connecting wires As required

THEORY:

The most basic arithmetic operation is the addition of two binary digits.  There are four possible elementary operations, namely,

0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = 102

The first three operations produce a sum of whose length is one digit, but when the last operation is performed the sum is two digits.  The higher significant bit of this result is called a carry and lower significant bit is called the sum.

A combinational circuit which performs the addition of two bits is called half adder.  The input variables designate the augend and the addend bit, whereas the output variables produce the sum and carry bits.

A combinational circuit which performs the arithmetic sum of three input bits is called full adder.  The three input bits include two significant bits and a previous carry bit.  A full adder circuit can be implemented with two half adders and one OR gate.

TRUTH TABLE:

 S.No INPUT OUTPUT A B S C 1. 0 0 0 0 2. 0 1 1 0 3. 1 0 1 0 4. 1 1 0 1

DESIGN:

From the truth table the expression for sum and carry bits of the output can be obtained as,
Sum, S = A  B
Carry, C = A . B

CIRCUIT DIAGRAM:

TRUTH TABLE:

 S.No INPUT OUTPUT A B C SUM CARRY 1. 0 0 0 0 0 2. 0 0 1 1 0 3. 0 1 0 1 0 4. 0 1 1 0 1 5. 1 0 0 1 0 6. 1 0 1 0 1 7. 1 1 0 0 1 8. 1 1 1 1 1

DESIGN:

From the truth table the expression for sum and carry bits of the output can be obtained as,

SUM = A’B’C + A’BC’ + AB’C’ + ABC
CARRY = A’BC + AB’C + ABC’ +ABC

Using Karnaugh maps the reduced expression for the output bits can be obtained as,

SUM

SUM = A’B’C + A’BC’ + AB’C’ + ABC = A  B  C

CARRY

CARRY = AB + AC + BC

CIRCUIT DIAGRAM:

PROCEDURE:

1. Connections are given as per the circuit diagrams.
2. For all the ICs 7th  pin is grounded and 14th pin is given +5 V supply.
3. Apply the inputs and verify the truth table for the half adder and full adder circuits.

RESULT:

The design of the half adder and full adder circuits was done and their truth tables were verified.