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Wednesday, October 12, 2011

BCD to 7 segment decoder using IC 7447



BCD to 7 segment decoder using IC 7447

Aim:   To observe the BCD to 7 segment decoder using IC7447

Apparatus:

1.      BCD to 7 segment decoder kit


Circuit Description:
                 
                            The 7447 decode the input data in the pattern indicated in the table-1 and segment identification as in fig-2. if the input data decimal Zero , a low signal applied to RBI blanks the display and causes a mutidigit display. For eg. By grounding the RBI of the highest order decoder and connecting it’s BI/RBO of the next lowest order decoder, etc, leading Zero’s will be suppressed. Similarly, by grounding RBI of the lowest order decoder and connecting it’s BI/RBO also serves as an unconditional blanking input. The internal NAND gate that generates the RBO signal has a resistive pull-up, as opposed to a totempole, and thus BI/RBO turns off all segment outputs. This
Blanking feature can be used to control display intensity by varying the duty cycle of the the blanking signal. A low signal applied to LT turns on all segment outputs provided that R1\RBO is not forced low


Circuit Diagram:






































           
Procedure:

  1. Switch ON the experimental kit by connecting the power card to the AC mains
  2. Set up 4 bit BCD data using the toggle switches shown in fig -1.
  3. The binary equivalent is indicated on the input LED’s. A logic 1 is represented by glow and a logic 0 by no glow.
  4. Observe the corresponding decimal number on the 7 – segment display.
  5. Change the input switches of A1, A2, A3, & A4 through all the 16 states and observe the display output.

















Tabular forms:




















Result:













Procedure:
Three input full subtractor: X1 and X2 are two logic inputs and Bin is the borrow input to find the difference D and borrow B outputs for all combinations of X1, X2, and Bin.
  1. Connect X1, X2 and Bin to three data input switches.
  2. Connect OR gate output and EX-OR gate output to output status.
  3. Connect the circuit as shown in figure 4.
  4. Set up data in X1, X2, and Bin by means of the input switches and fill up the table 4.
  5. Verify the result with the theoretical values.

Truth Table:







Result:
> -b� - e �� H � ys'>

NAND gate:










Realization of OR, AND, NOT, NOR gates by NAND gates
OR gate:







AND gate:






NOT gate:











NOR gate:








Procedure:
  1. Connect the trainer as shown in figures.
  2. Verify the working of OR gate, AND gate, NOT gate, NAND gate and NOR gate with the help of truth tables given.

Result:

1 comments:

Dhananjay . . . said...

here too ckt dia.
result,
truth table etc fields are empty.. plz make it visible.
thx adv.

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